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Add QSPI NOR flash driver for SF32LB #96085

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@gmarull gmarull commented Sep 16, 2025 •
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Add flash (QSPI NOR) driver for SF32LB

@gmarull gmarull requested a review from cameled September 16, 2025 13:21
@github-actions github-actions bot added manifest manifest-hal_sifli DNM (manifest) This PR should not be merged (controlled by action-manifest) labels Sep 16, 2025
@gmarull gmarull force-pushed the sf32lb52x-flash branch 3 times, most recently from ce5be5e to 7335cff Compare September 17, 2025 19:05
@zephyrproject-rtos zephyrproject-rtos deleted a comment from github-actions bot Oct 1, 2025
@gmarull gmarull removed the DNM (manifest) This PR should not be merged (controlled by action-manifest) label Oct 1, 2025
@gmarull gmarull force-pushed the sf32lb52x-flash branch 3 times, most recently from 5218a60 to 003a034 Compare October 1, 2025 12:10
@gmarull gmarull marked this pull request as ready for review October 1, 2025 12:10
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gmarull commented Oct 1, 2025

Questions for @rabbitsaviola

  • Please review the driver in general
  • DMA code is not placed in RAM, but it's called from flash_sf32lb_mpi_qspi_nor_write, is it okay?
  • Clarify in general what is strictly needed to be placed in RAM
  • Clarify why using write chunk lengths > FIFO size does not work (L324); use, e.g., teslabs@43a7ae6 to check

@gmarull gmarull added the DNM This PR should not be merged (Do Not Merge) label Oct 1, 2025
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  • DMA code is not placed in RAM, but it's called from flash_sf32lb_mpi_qspi_nor_write, is it okay?

it's ok that DMA code is not placed in RAM as sequence command mode used.

  • Clarify why using write chunk lengths > FIFO size does not work (L324); use, e.g., teslabs@43a7ae6 to check

write doesn't work when chunk_len > FIFO size is because RBSIZE is set to 3 by L535. If RBSIZE is 0, chunk_len=128byte works well.

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gmarull commented Oct 14, 2025 •
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last push: moved flash nor parameters to module-level variable, same as in spi_nor.c (and fixed write block size).

@gmarull gmarull requested a review from fabiobaltieri October 14, 2025 15:28
@gmarull gmarull force-pushed the sf32lb52x-flash branch 2 times, most recently from 178403c to 8274aca Compare October 14, 2025 18:59
JarmouniA
JarmouniA reviewed Oct 14, 2025
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@gmarull gmarull requested a review from JarmouniA October 14, 2025 20:04
decsny
decsny reviewed Oct 15, 2025
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dts/bindings/mtd/jedec,qspi-nor.yaml

description: Generic NOR flash on QSPI bus

compatible: "jedec,qspi-nor"
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why is this new binding needed

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see commit description, we cannot use jedec,spi-nor because it's tied to SPI buses, but, in Zephyr, QSPI controllers live in a limbo.

gmarull added 10 commits October 15, 2025 17:05
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dts: bindings: mtd: add sifli,sf32lb-mpi-qspi-nor
8b4ca82 
Add compatible for SiFli SF32LB MPI operating as QSPI NOR controller.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
dts: arm: sifli: sf32lb52x: adjust mpi1/2 defaults
d1202da 
Compatible should be set at board level, depending on how MPI IP is used
(e.g. NOR, NAND, PSRAM).

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
dts: bindings: memory-controllers: drop sifli,sf32lb-mpi
b213b99 
No longer used.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
dts: bindings: mtd: add jedec,qspi-nor
71b651b 
Ideally we should be able to just use jedec,spi-nor (to keep Linux
compatibility), but, QSPI controllers live in a limbo in Zephyr. Adding
this binding won't make things worse than they are.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
drivers: flash: spi_nor: add SPI_NOR_CMD_BE_32K_4B
09d12d1 
Command was missing.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
scripts: kconfig: kconfigfunctions: add dt_node_reg_addr_by_name_hex
0981e5f 
So we can obtain a register address (as hex) given its name.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
soc: sifli: sf32: sf32lb52x: configure flash base address
1c29290 
Take it from the chosen flash node parent (MPI controller) 'nor'
register, which contains the memory mapped address for the NOR flash.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
drivers: flash: sf32lb_mpi_qspi_nor: add initial driver
632cdbf 
Initial driver for the SF32LB MPI accessing QSPI NOR flash devices.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
boards: sf32lb52_devkit_lcd: adjust memory and QSPI NOR parameters
b51bf0c 
So that flash driver can be used (MPI2 works in QSPI mode).

Signed-off-by: Gerard Marull-Paretas <[email protected]>
@gmarull
samples: drivers: jesd216: add support for SF32LB
3bfb8ae 
Allow obtaining SFDP parameters using SF32LB driver.

Signed-off-by: Gerard Marull-Paretas <[email protected]>
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Quality Gate Passed Quality Gate passed

Issues
1 New issue
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

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gmarull commented Oct 15, 2025

last pushes:

  • qspi_nor_read_fifo pushed to RAM (was causing issues when e.g. reading JEDEC ID, FYI @rabbitsaviola)
  • Fixed incorrect flash size (128mbit)

cameled
cameled approved these changes Oct 15, 2025
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LGTM, test pass on my board.

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